There is a demand for faster, higher capacity, random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) devices are typically used as the main memory in computer systems. Although the operating speed of the DRAM has improved over the years, the speed has not reached that of the processors used to access the DRAM.
Synchronous dynamic random access memory (SDRAM) has been developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the system clock. That is, input and output data of the SDRAM are synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Double data rate (DDR) SDRAMs and second generation DDR SDRAMs, known as DDR II SDRAMs, are being developed to provide twice the operating speed of the conventional SDRAM. These devices allow data transfers on both the rising and falling edges of the system clock and thus, provide twice as much data as the conventional SDRAM.
It is desirable that DDR SDRAM devices are operated in accordance with industry standards, such as the Stub Series Terminated Logic for 2.5V (SSTL—2) standard. By adhering to industry standards, the DDR SDRAM devices are assured of being compatible with other industry components that also adhere to the standards. This way, components from different manufacturers may be integrated into the same system without adversely impacting the performance of the system.
Current standards dictate that DDR SDRAM devices have “low” power operations such as e.g., power-down and self-refresh operations. These low power operations are initiated when a clock enable control signal (CKE), which activates and deactivates an internal clock of the DDR SDRAM, is received having a value that disables the internal clock. During a power-down condition, the specification indicates that all input buffers should be disabled with the exception of input buffers used for the clock enable CKE and differential clock input signals CK, CK#. During self-refresh, the specification indicates that all input buffers should be disabled with the exception of input buffers used for the clock enable signal CKE. The enabled input buffers, however, draw current, which is undesirable.
Moreover, DDR SDRAM devices use a specified reference voltage (Vref) in its input receiver and buffers. The reference voltage Vref is usually connected to a first input of a differential amplifier while a second input of the amplifier is connected to command, address or data lines. The reference voltage Vref is used to determine whether the received command, address or data has a value of logic 0 or logic 1. The amplifier, however, draws current. It is desirable to reduce the current being drawn in the low power operating modes.
Furthermore, it is desirable to ground or float the reference voltage Vref in the low power operating mode to reduce the overall power consumption of the system that the DDR SDRAM device is used in during the low power modes. Grounding or floating the reference voltage Vref, however, adversely affects the operation of the DDR SDRAM's differential amplifiers, used in the remaining activated buffers, since a small input signal, noise or other glitch can cause the differential amplifier to output a logic 1 instead of a logic 0. For example, if noise were present on the differential amplifier input connected to receive the clock enable signal CKE, the amplifier will output a logic 1 instead of 0, which takes the SDRAM out of the low power mode because the device thinks that a clock enable signal CKE with a value enabling the internal clock has been received. Moreover, the device is susceptible to being repetitively placed into and taken out of the low power mode if there is noise or some other glitch in the device. These scenarios are undesirable and are contrary to the industry standards.
Another technique uses additional TTL logic, such as a TTL buffer or inverter to detect when the clock enable signal CKE is received during low power modes. The TTL buffer does not rely on a comparison to the reference voltage Vref, but has other problems. For example, the clock enable signal CKE is specified by the industry standard as a differential signal, but the buffer is not a differential buffer. If noise were present on the line carrying the clock enable signal CKE to the TTL buffer, the buffer trip point could be reached causing the buffer to output a logic 1 instead of 0, which takes the SDRAM out of a low power mode. This is undesirable and is contrary to the industry standards.
Accordingly, there is a need and desire for an improved method and apparatus that reduces power when operating a DDR SDRAM in a low power operating mode such as power-down or self-refresh.